The History of the Transistor and Moore's Law

The transistor is the foundational building block of modern electronics, functioning as a microscopic switch or amplifier that controls the flow of electrical current.^[26] Before its invention, electronic systems relied on vacuum tubes, which were bulky, fragile, and consumed vast amounts of power. The transition from vacuum tubes to solid-state transistors enabled the miniaturization of electronic circuits, leading directly to the development of the integrated circuit and the microprocessor. This hardware evolution provided the physical infrastructure for the digital age, transforming computing from room-sized machines used for artillery calculations into ubiquitous devices embedded in nearly every aspect of modern infrastructure.^[27]

The trajectory of this technological expansion was defined by Moore's Law. In 1965, Moore predicted the number of components would double every year; he revised this to every two years in 1975.^[28] Rather than a law of physics, this principle functioned as an economic and engineering roadmap. It established a predictable cadence for the semiconductor industry, aligning the research and development cycles of materials scientists, lithography equipment manufacturers, and chip designers. By targeting exponential increases in transistor density, the industry simultaneously achieved exponential improvements in computational speed and reductions in cost per function.

Maintaining this trajectory required continuous engineering breakthroughs. As transistors shrank from millimeter scales to nanometer dimensions, engineers confronted severe physical constraints, including quantum tunneling, heat dissipation, and the limits of optical resolution. Overcoming these barriers necessitated fundamental changes in transistor architecture, shifting from early point-contact and bipolar junction designs to metal-oxide-semiconductor field-effect transistors (MOSFETs), and eventually to three-dimensional structures like FinFETs and gate-all-around (GAA) designs. The history of the transistor is a record of overcoming successive physical limitations to sustain the economic engine of Moore's Law.^[29]

The Pre-Transistor Era and Vacuum Tubes

During the first half of the twentieth century, electronic amplification and switching were performed by thermionic valves, commonly known as vacuum tubes. Invented by John Ambrose Fleming in 1904 and improved by Lee de Forest with the addition of a control grid in 1906, the vacuum tube operated by boiling electrons off a heated cathode in a glass vacuum chamber. While effective for early radio and telephony, vacuum tubes possessed severe inherent constraints. They required large amounts of power to heat the filament, generated substantial waste heat, and suffered from high failure rates due to filament burnout and vacuum leaks. Early computers, such as the ENIAC completed in 1945, utilized approximately 17,468 vacuum tubes, consumed 150 kilowatts of electricity, and experienced frequent hardware failures that limited continuous operation.

The theoretical foundation for a solid-state alternative existed decades before it could be manufactured. In 1925, physicist Julius Edgar Lilienfeld filed a patent for a method of controlling electric current in a solid, describing the basic principle of a field-effect transistor Julius Edgar Lilienfeld, "Method and Apparatus for Controlling Electric Currents"^[1]. However, the materials science of the 1920s could not produce semiconductor crystals with the extreme purity required to demonstrate the effect. Semiconductors, such as germanium and silicon, possess electrical conductivity between that of a conductor and an insulator. Their conductivity can be manipulated by introducing specific impurities, a process called doping.

The catalyst for practical semiconductor development was World War II. The military required compact, reliable microwave detectors for radar systems, leading to heavily funded research into purifying germanium and silicon crystals. This wartime research established the metallurgical techniques necessary to control semiconductor properties, providing the raw materials for post-war solid-state physics.

The Invention of the Transistor at Bell Labs

Following World War II, American Telephone and Telegraph (AT&T) faced a major infrastructure constraint. The company needed to expand its long-distance telephone network, but vacuum tube repeaters were too unreliable and power-hungry for widespread deployment in transcontinental cables. Mervin Kelly, the director of research at Bell Telephone Laboratories, formed a solid-state physics group tasked with creating a reliable, solid-state amplifier. The group was led by William Shockley and included experimental physicists John Bardeen and Walter Brattain.

On December 16, 1947, Bardeen and Brattain successfully demonstrated the first working transistor, known as the point-contact transistor. They achieved this by pressing two closely spaced gold foil contacts onto a slab of germanium. When a small current was applied to one contact (the emitter), it modulated a larger current flowing through the other contact (the collector) Computer History Museum, "Invention of the Point-Contact Transistor"^[2]. The device amplified the input signal by a factor of 100. Bardeen and Brattain filed a patent for the device, which Bell Labs publicly announced in 1948 ^[3].

While groundbreaking, the point-contact transistor was difficult to manufacture reliably because it depended on the precise physical placement of metal wires on the crystal surface. It was also electrically noisy and fragile. Shockley, frustrated by his exclusion from the initial point-contact patent, worked independently to design a superior architecture. In early 1948, he formulated the theory of the bipolar junction transistor (BJT). Instead of relying on surface contacts, Shockley's design used a continuous crystal with three distinct regions of doped semiconductor material (either N-P-N or P-N-P) William Shockley, "Circuit Element Utilizing Semiconductive Material"^[4].

The BJT relied on the physics of the p-n junction, where the interface between positively doped (p-type) and negatively doped (n-type) materials creates a depletion region that controls electron flow. Manufacturing a BJT required growing a single crystal with alternating doped layers, a formidable metallurgical challenge. In 1951, Bell Labs chemists Gordon Teal and Morgan Sparks successfully grew the first working junction transistor. The BJT proved far more reliable and easier to mass-produce than the point-contact design, becoming the standard transistor architecture for the next decade Nobel Prize Outreach, "The Nobel Prize in Physics 1956"^[5]. Facing an antitrust lawsuit from the United States government, AT&T began licensing its transistor patents for a $25,000 flat fee in 1952; it was the 1956 consent decree that forced them to license existing patents royalty-free, directly catalyzing the global semiconductor industry.

Commercialization and the Silicon Shift

The earliest commercial transistors were made of germanium. Germanium was easier to purify and had a lower melting point than silicon, making it easier to work with using 1950s technology. However, germanium transistors suffered from a severe physical limitation: they experienced excessive current leakage and ceased to function at temperatures above 75 degrees Celsius. This made them unsuitable for military and aerospace applications, which demanded operation in extreme environments.

Gordon Teal left Bell Labs to join Texas Instruments (TI) in Dallas, Texas. In 1954, Teal's team developed the first commercial silicon transistor Computer History Museum, "Silicon Transistors Offer Superior Operating Characteristics"^[6]. Silicon possesses a larger bandgap than germanium, allowing it to function at much higher temperatures. Although silicon was harder to purify and required higher processing temperatures, its superior thermal stability and abundance in the Earth's crust caused the industry to rapidly abandon germanium.

Simultaneously, the geographic center of the industry began to shift to the Santa Clara Valley in California. In 1956, William Shockley founded Shockley Semiconductor Laboratory in Mountain View to commercialize silicon transistors. While Shockley was a brilliant physicist, his erratic and authoritarian management style alienated his staff. In 1957, eight of his top scientists and engineers, including Robert Noyce and Gordon Moore, resigned. Dubbed the "Traitorous Eight" by Shockley, they secured funding from Sherman Fairchild to establish Fairchild Semiconductor.

At Fairchild, physicist Jean Hoerni solved a major reliability problem regarding transistor junctions. Early junction transistors were manufactured using a mesa process, which left the p-n junctions exposed to ambient air and contaminants, leading to electrical degradation. In 1959, Hoerni invented the planar process. He utilized a layer of silicon dioxide (glass) grown over the silicon wafer as an insulator. By etching microscopic windows into the oxide layer, impurities could be diffused into the silicon below to create the transistor junctions, while the oxide protected the rest of the surface Jean Hoerni, "Method of Manufacturing Semiconductor Devices"^[7]. The planar process left the final transistor completely flat and protected by a passivating oxide layer Computer History Museum, "Invention of the Planar Manufacturing Process"^[8]. This technique allowed multiple transistors to be printed simultaneously on a single wafer using photographic methods, establishing the fundamental manufacturing paradigm still used in semiconductor fabrication today.

The Integrated Circuit and the MOSFET

The Monolithic Integrated Circuit

By the late 1950s, engineers faced the "tyranny of numbers." As computers required tens of thousands of transistors, wiring them together individually by hand became economically and physically impossible due to the sheer number of solder joints, which increased the probability of failure.

In 1958, Jack Kilby at Texas Instruments demonstrated the first integrated circuit (IC). Kilby built multiple components (transistors, resistors, and capacitors) on a single piece of germanium. However, Kilby's design still required tiny gold wires to connect the components, which did not solve the mass-production problem Jack Kilby, "Miniaturized Electronic Circuits"^[9].

In 1959, Robert Noyce at Fairchild Semiconductor realized that Hoerni's planar process could be used to integrate the connections directly onto the chip. Noyce deposited a layer of metal (aluminum) over the silicon dioxide insulator and etched it to form the wires connecting the underlying transistors Robert Noyce, "Semiconductor Device-and-Lead Structure"^[10]. This created the first monolithic integrated circuit, where both the components and their interconnections were manufactured simultaneously on a single silicon substrate Encyclopaedia Britannica, "Integrated Circuit"^[11].

The Metal-Oxide-Semiconductor Field-Effect Transistor

Despite the success of the IC, bipolar junction transistors had a fundamental drawback: they were current-controlled devices. A BJT requires a continuous flow of current into its base to remain in the "on" state, which consumes steady power and generates heat. In addition, BJTs were difficult to scale down in size due to their complex vertical structures.

In 1959, Mohamed Atalla and Dawon Kahng at Bell Labs invented the metal-oxide-semiconductor field-effect transistor (MOSFET) Dawon Kahng, "Electric Field Controlled Semiconductor Device"^[12]. The MOSFET realized the field-effect concept proposed by Lilienfeld in 1925. It consisted of a silicon channel between a source and a drain, covered by a thin insulating layer of silicon dioxide, topped with a metal gate. Because the gate was electrically insulated from the channel, the MOSFET was a voltage-controlled device. Applying a voltage to the gate created an electric field that drew charge carriers into the channel, allowing current to flow from source to drain Computer History Museum, "Metal-Oxide-Semiconductor (MOS) Transistor Demonstrated"^[13].

The MOSFET consumed almost no static current through the gate, was much smaller than a BJT, and required fewer manufacturing steps. In 1963, Frank Wanlass at Fairchild Semiconductor patented complementary MOS (CMOS), which paired p-type and n-type MOSFETs in a circuit where only one type was active at a time Computer History Museum, "Complementary MOS Circuit Configuration is Invented"^[14]. CMOS circuits consumed significant power only during the brief moment of switching states, reducing standby power consumption to nearly zero. This power efficiency made CMOS the dominant technology for high-density integrated circuits.

The Formulation of Moore's Law and Dennard Scaling

In 1965, Electronics magazine asked Gordon Moore, then the director of research at Fairchild, to predict the future of semiconductor components over the next decade.^[30] Moore noted that the number of components on an integrated circuit had doubled every year since the invention of the planar process in 1959. He extrapolated this trend, predicting that by 1975, a single silicon chip would contain 65000 components Gordon E. Moore, "Cramming More Components Onto Integrated Circuits"^[15].

In 1975, at the IEEE International Electron Devices Meeting, Moore revised his observation, predicting a doubling of transistor density approximately every two years Gordon E. Moore, "Progress in Digital Integrated Electronics"^[16].^[31] This observation became known as Moore's Law Encyclopaedia Britannica, "Moore's Law"^[17]. It functioned as a self-fulfilling prophecy. To prevent falling behind competitors, semiconductor companies structured their capital investments and research timelines to meet Moore's predicted cadence. The industry eventually formalized this coordination through the International Technology Roadmap for Semiconductors (ITRS), which synchronized the efforts of chemical suppliers, optics manufacturers, and chip fabricators Wikipedia, "International Technology Roadmap for Semiconductors"^[18].

The technical mechanism that allowed Moore's Law to translate into performance gains was articulated in 1974 by Robert Dennard at IBM. Dennard scaling, or constant-field scaling, established that as transistors shrink in physical dimensions, their voltages and currents scale downward proportionally, while the electric field remains constant ^[19]. According to Dennard's equations, if a transistor's linear dimensions are reduced by a factor of 0.7, its area decreases by half. The capacitance and voltage also decrease by 0.7. Consequently, the transistor switches 40 percent faster, and the power consumed per transistor drops by 50 percent. This meant that the power density of the chip remained constant. Dennard scaling allowed chipmakers to double the number of transistors and increase the clock frequency with every generation without increasing the overall power consumption of the chip IBM, "Dennard Scaling".

The Microprocessor Era

The ability to integrate thousands of MOSFETs onto a single chip enabled the creation of the microprocessor, a complete central processing unit (CPU) on a single piece of silicon. In 1968, Robert Noyce and Gordon Moore left Fairchild to found Intel Corporation. In 1971, Intel released the 4004, the first commercial microprocessor. Designed by Federico Faggin, Ted Hoff, and Masatoshi Shima, the 4004 was a 4-bit processor containing 2250 transistors built on a 10-micrometer process Computer History Museum, "Microprocessor Integrates CPU Function Onto a Single Chip"^[20].

The microprocessor standardized computing hardware. Instead of designing custom logic circuits for different machines, engineers could use a standard microprocessor and alter its software. Intel followed the 4004 with the 8-bit 8008 in 1972, before releasing the 8080 in 1974, which contained 4500 transistors and became the foundation for early personal computers Computer History Museum, "8-Bit Microprocessor Introduced". In 1978, Intel introduced the 16-bit 8086, establishing the x86 instruction set architecture that continues to dominate desktop and server computing today IEEE, "The x86 Microprocessor Architecture"^[21].

During the 1970s, most microprocessors used n-channel MOS (NMOS) technology because it was faster and denser than early CMOS. However, as transistor counts reached the hundreds of thousands in the 1980s, the static power dissipation of NMOS caused chips to overheat. The industry was forced to transition entirely to CMOS manufacturing. While CMOS required more complex fabrication steps to create both p-type and n-type wells on the same substrate, its near-zero static power consumption was mandatory to sustain Moore's Law into the megahertz and gigahertz eras.

Deep Submicron Scaling and Lithography Constraints

As transistor feature sizes shrank below 1 micrometer into the deep submicron regime during the late 1980s and 1990s, the semiconductor industry encountered severe physical and optical barriers. The manufacturing of integrated circuits relies on photolithography, where light is projected through a photomask to expose chemical photoresists on the silicon wafer. The resolution of the printed features is limited by the wavelength of the light used.

Early lithography used visible light, but as features shrank, manufacturers shifted to ultraviolet (UV) light using mercury-vapor lamps (365 nanometers). By the 2000s, the industry utilized deep ultraviolet (DUV) excimer lasers, specifically argon fluoride (ArF) lasers producing light at 193 nanometers. When transistor features needed to shrink below 193 nanometers, the wavelength of the light was larger than the features being printed, causing diffraction and blurring. To bypass this optical limit, engineers developed immersion lithography, placing a layer of highly purified water between the lens and the wafer to increase the numerical aperture and refractive index. They also employed multiple patterning, splitting dense circuit layouts across two or more photomasks to print features smaller than the optical resolution limit.

Simultaneously, the physics of the transistor began to break down. Around 2005, Dennard scaling collapsed Wikipedia, "Dennard scaling"^[22]. As the insulating gate oxide was scaled down to a thickness of just a few atomic layers (around 1.2 nanometers), electrons began to undergo quantum tunneling directly through the insulator, creating massive leakage currents. In addition, as the distance between the source and drain (the channel length) decreased, the gate lost electrostatic control over the channel. This phenomenon, known as short-channel effects, meant the transistor could not be fully turned off, resulting in subthreshold leakage.

Because of these leakage currents, power density was no longer constant. Increasing the clock speed caused the chips to generate unmanageable amounts of heat. Consequently, CPU clock frequencies stalled at around 3 to 4 gigahertz. To continue delivering performance improvements without melting the silicon, the industry shifted from single-core frequency scaling to multicore architectures, placing multiple independent processing units on a single chip to process tasks in parallel. To address gate leakage, manufacturers replaced the traditional silicon dioxide gate insulator with high-k dielectrics (such as hafnium oxide) and replaced the polysilicon gate electrode with metal, restoring the gate's ability to block tunneling currents.

3D Transistors and the Modern State of Scaling

To combat short-channel effects and continue increasing transistor density, the fundamental two-dimensional planar structure of the MOSFET had to be abandoned. In 1999, a research team led by Chenming Hu at the University of California, Berkeley, developed the FinFET (fin field-effect transistor) Nature Electronics, "The FinFET Semiconductor Technology". In a FinFET, the silicon channel is raised out of the substrate to form a thin, three-dimensional fin. The gate is draped over the fin, wrapping around it on three sides. This 3D geometry vastly improved the gate's electrostatic control over the channel, drastically reducing leakage current and allowing the transistor to switch faster at lower voltages Wikipedia, "FinFET"^[23]. Intel was the first to commercialize FinFET technology. Intel announced its 22-nanometer 3D Tri-Gate (FinFET) technology in 2011, but Ivy Bridge processors were not released until 2012. Intel, "Gordon Moore's Law"^[24].^[32]

As FinFETs scaled down through the 14-nanometer, 10-nanometer, and 7-nanometer nodes, the fins became incredibly tall and thin, leading to structural instability and diminishing returns. To scale further, the industry transitioned to Gate-All-Around (GAA) transistors, also known as nanosheet or nanowire transistors. In a GAAFET, the silicon channel is divided into multiple horizontal sheets stacked on top of each other, and the gate material completely surrounds each sheet on all four sides, providing maximum electrostatic control. Samsung Electronics became the first to implement GAA architecture in high-volume manufacturing with its 3-nanometer process in 2022 .

The fabrication of these sub-10-nanometer structures required a revolutionary leap in lithography. After decades of development and billions of dollars in research, ASML commercialized Extreme Ultraviolet (EUV) lithography. EUV uses light with a wavelength of 13.5 nanometers. Because all materials, including glass, absorb EUV light, it cannot be focused with traditional lenses. Instead, EUV machines use a complex system of ultra-smooth Bragg reflectors (mirrors) in a high vacuum. The 13.5-nanometer light is generated by firing a high-power carbon dioxide laser at microscopic droplets of molten tin falling through a vacuum chamber, turning the tin into a plasma that emits EUV radiation ASML, "EUV lithography systems". EUV enabled foundries like Taiwan Semiconductor Manufacturing Company (TSMC) to achieve volume production of 5-nanometer and 3-nanometer chips TSMC, "TSMC Celebrates 3nm Volume Production"^[25].

Today, Moore's Law faces severe economic and physical constraints. The cost of constructing a leading-edge semiconductor fabrication plant now exceeds 20 billion dollars, driven by the extreme cost of EUV lithography machines and the complexity of the manufacturing process. This massive capital requirement has consolidated the leading-edge foundry market to just three companies: TSMC, Samsung, and Intel. While transistor density continues to increase, the cost per transistor has plateaued, altering the economic calculus that drove the industry for fifty years.

Physically, the dimensions of modern transistors are approaching the atomic spacing of silicon, which is approximately 0.2 nanometers. To maintain performance growth in the face of these limits, the industry has adopted advanced packaging techniques. Rather than relying solely on shrinking transistors on a single monolithic die, manufacturers now design "chiplets", smaller specialized chips manufactured on different process nodes, which are then stitched together using high-density interconnects in 2.5D and 3D packages. The history of the transistor, from the macro-scale vacuum tube to the atomic-scale gate-all-around nanosheet, reflects a continuous engineering battle against physical limits, resulting in the most complex manufacturing processes in human history.